The present invention relates generally to semiconductor devices and more particularly to analog and digital MIM capacitors and methods for fabricating such in the manufacture of semiconductor device products.
Capacitors are employed in digital and analog devices for a variety of purposes, including storing electrical charge, filtering, blocking DC voltage levels, and stabilizing power supplies (e.g., decoupling switching noise from DC supplies). Typical capacitors used in semiconductor devices may have the structure of a metal oxide semiconductor (MOS) type, a P-N junction type, a polysilicon-insulator-polysilicon (PIP) type, a metal-insulator-metal (MIM) type, etc., wherein the type of capacitor employed typically depends on the application (e.g., analog or digital) and desired response characteristics of the device.
PIP capacitors suffer from capacitance variations caused by the doping characteristics of the polysilicon capacitor electrode plates, and as such, these devices exhibit fairly large changes in the capacitance as a function of applied voltage. Hence these devices have a large voltage coefficient of capacitance (VCC), typically measured in parts per million per volt (ppm/V). In addition, parasitic effects are seen in MOS type transistors where the capacitor is located proximate the substrate. MIM type capacitors may be advantageously fabricated in upper interconnect layers of a semiconductor device wafer to mitigate such parasitic effects. MIM capacitors are further desirable, since the electrode plates are fabricated from conductive metal materials, whereby the polysilicon doping issues and polysilicon depletion associated with PIP capacitors are avoided.
Voltage dependent capacitance effects are generally more detrimental in analog capacitors than in decoupling capacitors. Thus, in semiconductor devices having both analog and digital circuitry (e.g., sometimes referred to as mixed-signal devices), some capacitors have different design performance criteria than others. In this regard, mixed-signal devices generally employ decoupling capacitance to reduce power supply transients associated with switching transistors, as well as analog capacitors for filtering and other types of analog circuits.
Decoupling capacitors (e.g., digital capacitors) require high capacitance density (e.g., measured in fF/um2) in order to minimize the amount of device area devoted to decoupling. In some cases, capacitance densities of 10 fF/um2 or more are desired to minimize the die area occupied by decoupling capacitors, particularly as higher clock speeds (e.g., transistor switching speeds) dictate increased decoupling capacitance requirements. However, decoupling capacitors generally are not as sensitive to the dependence of capacitance on voltage as are analog capacitors. For instance, a decoupling capacitor connected between a power supply rail and ground will not see large fluctuations in applied voltage during normal operations (e.g., apart from fast transient switching noise in digital circuits). Thus, for a decoupling capacitor designed to decouple high frequency noise from a 3 V DC supply, the difference in capacitance at 1 V is relatively unimportant.
Conversely, analog circuits do not demand such high capacitance densities, wherein densities of around 3 fF/um2 or less may be used. However, analog circuits are much less tolerant of capacitance variations during operation than are digital circuits. For example, if the impedance of the capacitor is not reasonably predictable or consistent across the range of expected applied voltages, the circuit performance could be different for different applied voltages, and consequently, the performance of the analog circuit may be unsatisfactory. Thus, whereas decoupling capacitors can be successfully employed with relatively large fluctuations in capacitance with changes in applied voltage, analog capacitors are typically designed to have VCC specifications in a range of about 300 ppm/V or less.
These divergent capacitor design goals often lead to separate processing operations to form digital (e.g., decoupling) and analog capacitors in the manufacture of semiconductor devices, particularly in mixed-signal type devices. Separate capacitor dielectrics have conventionally been employed since the VCC coefficients typically get smaller as dielectric film thickness is increased, while the capacitance density is reduced for thicker dielectrics. Some processes fabricate analog and decoupling MIM type capacitors in separate interconnect levels or layers, while others form different dielectric layers in the same interconnect level for the analog and digital MIM capacitors. In either case, multiple masks and process steps are required to separately form the decoupling and analog capacitors. It is a continuing goal to reduce or streamline the number of such processing steps, so as to increase product throughput and reduce product cost in the manufacture of semiconductor devices. Accordingly, there is a need for capacitor structures and processing methods by which analog and decoupling capacitors can be fabricated to accommodate the different performance requirements with respect to VCC, leakage current, and capacitance density, and which reduce the number of processing steps required for capacitor fabrication.
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later. The invention relates to semiconductor devices and methods for making the same in which a single dielectric layer is used to form metal-insulator-metal (MIM) decoupling capacitors and analog capacitor segments. Analog capacitors are formed by coupling analog capacitor segments in series with one another. High k dielectric material or ferroelectric material may be used to form the single dielectric layer for the analog and decoupling capacitors, and the polarities of the analog capacitor segments may be reversed to effectively reduce asymmetric effects related to applied voltage. In this manner, a streamlined manufacturing process may be achieved, which produces capacitors adapted for the different requirements of analog and decoupling (e.g., digital) capacitors.
In accordance with one aspect of the invention, a method of fabricating capacitors in a mixed-signal semiconductor device is provided, which comprises forming a dielectric layer above a wafer, forming a decoupling capacitor and a plurality of analog capacitor segments using the dielectric layer, and coupling two or more of the analog capacitor segments in series to form an analog capacitor. The dielectric layer may be a high k dielectric material, such as having a dielectric constant k greater than about 8, for example, tantalum oxide (TaO), or ferroelectric material, for example, Pb(Zr,Ti)O3 (PZT), (Ba,Sr)TiO3 (BST), SrTiO3 (STO) and SrBi2TA2O9 (SBT), BaTiO3 (BTO), (Bil-xLax) 4Ti3O12 (BLT), or other ferroelectric material, deposited over a conductive (e.g., metal) bottom electrode layer. A top electrode layer is then formed over the dielectric, wherein the top and bottom electrode layers may comprise any suitable material, such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), iridium (Ir), iridium oxide (IrO), or others.
The top and bottom electrode layers and the dielectric layer are then patterned using a single mask, so as to form decoupling capacitors and analog capacitor segments in a small number of processing steps in the manufacturing flow. The patterning provides one or more decoupling capacitors, as well as a number of analog capacitor segments separated from one another, individually comprising unetched portions of the bottom electrode layer, the dielectric layer, and the top electrode layer, wherein the dielectric material in the decoupling capacitor and the plurality of analog capacitor segments are of substantially the same thickness.
The analog capacitor segments are series coupled to form analog capacitors having the desired lower effective capacitance density (fF/um2), wherein the individual segments may be interconnected in reverse polarity relationship to provide substantially symmetric capacitance vs. voltage and leakage current performance characteristics. For example, the analog capacitor segments may be connected in series by electrically connecting bottom electrode portions of first and second analog capacitor segments to one another or by electrically connecting top electrode portions of first and second analog capacitor segments to one another.
Any number of such segments may be connected in this manner to form analog capacitors of a desired capacitance value. In one example, four such segments are coupled through electrically connecting bottom electrode portions of first and second analog capacitor segments to one another, electrically connecting top electrode portions of second and third analog capacitor segments to one another, and electrically connecting bottom electrode portions of third and fourth analog capacitor segments to one another to form an analog capacitor. In this manner, the design parameters for both decoupling (e.g., digital) capacitors and analog capacitors may be met, while reducing the total number of processing steps (e.g., and hence the cost) in manufacturing mixed-signal and other types of semiconductor devices.
In another aspect of the invention, a semiconductor device is provided, which comprises an analog capacitor having first and second analog capacitor segments coupled in series, wherein the first and second analog capacitor segments comprise first and second portions of a dielectric layer, respectively, and a decoupling capacitor comprising a third portion of the dielectric layer. The first and second analog capacitor portions may be coupled in reverse polarity relationship to one another, so as to provide a resulting analog capacitor having a substantially symmetrical VCC and leakage current performance with respect to applied voltage, such as by coupling top electrode portions thereof together, or by coupling bottom electrode portions thereof together. The dielectric layer used to form the decoupling capacitor and the analog capacitor segments may comprise a high k dielectric material, such as TaO material or ferroelectric materials, wherein the top and bottom electrodes may be fashioned from TiN, TiAlN, Ir, IrO, or other metal materials.
To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.